Many liquid crystal displays (LCDs) and organic light emitting diode displays (OLEDs) use an active-matrix scheme to access the display's array of pixels. Early displays used row- and column-driver integrated circuits to access the rows and columns of the active matrix. More recently, the row driver function has been implemented on the display glass itself, eliminating the need for a printed circuit board (PCB) along one side of the display. Displays of this type require a level shifter to translate the logic-level signals generated by the timing controller (typically a few volts) to the higher voltages required by the display panel (typically −5 V to −10 V for the low levels and 20 V to 30 V for the high levels). FIG. 1 is a block diagram of such an LCD control system 100. The active matrix display 110 of FIG. 1 can be an LCD display or an OLED display. The column driver IC 130 drives the columns of the active matrix display 110. The row driving function is implemented by row driving functionality 120 on the display glass itself. In some implementations, the row drivers are referred to as gate drivers. The terms “row driver” and “gate driver” will be used interchangeably herein to refer to the same functionality and neither term should be construed to be limited to a particular implementation. The timing controller 140 generates timing control signals for the column drivers 130 and row driving functionality 120. The level shifter 150 translates the logic-level signals generated by the timing controller 140 to the higher voltages needed by the row driving functionality of the display 110. LCD systems that use this type of scheme are variously referred to as gate-in-panel (GIP) systems, amorphous silicon gate driver (ASG) systems, and gate driver-on-array (GOA) systems. All of these names refer to displays using essentially the same technology.
In current LCD systems, the timing controller 140 provides multiple input signals to the level shifter 150, which translates them into a number of clock signals (typically four or eight) and control signals (typically two or four) for the gate driving circuitry 120 embedded in the display glass 110. In the simplest implementation of this scheme, each channel in the level shifter 150 comprises one input and one output, and the timing controller 140 must generate a control signal for each channel. This approach is simple, but requires a high pin-count in both the timing controller 140 and the level shifter 150, and a large number of PCB traces between the two. Furthermore, any changes required to the output signals of the level shifter require the timing controller 140 to be changed, which is not easy to do.
In current state-of-the-art displays, the timing controller 140 encodes the information for the display in a reduced number of signals, and the level shifter 150 contains a state machine that decodes the information and uses it to control its outputs. This approach requires a lower pin-count in the timing controller 140 and level shifter 150 and fewer PCB connections between the two than the previous solution, but it still suffers from a number of limitations. One such limitation is that the output signal generation is defined by a fixed state machine and cannot be changed without design modifications to the level shifter 150 or the timing controller 140. Also, the number of PCB traces between the timing controller 140 and the level shifter 150 is still higher than display designers would like. In many display applications, PCB real estate is at a premium and, for cost or PCB thickness reasons, the number of PCB layers is limited. In addition, the rigidity of the fixed state machine system limits product design cycle-time, especially when changes to the LCD panel are made that may require different drive schemes. Furthermore, high-volume end-equipment often uses LCD display panels from multiple sources, and a number of level shifter variants may be required to accommodate them all. This typically results in higher component and manufacturing cost.